The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages that receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Package development with each generation continues in complexity with continued process evolution and smaller more dense packages. Ball Grid Array (BGA) packages have decreased in ball pitch where 0.5 mm pitch is becoming common. Trace pitch on substrates are found in many products to 25 um. As dimensions scale the difficulties with noise and impedance control and variance become greater. Increased interconnect densities with future silicon technologies increase at a faster rate than package substrate interconnect density. With cost and footprint size a major consideration especially in the development of new mixed signal and RF products, the use and availability from suppliers of Chip Scale Packaging (CSP) on Molded Matrix Array Packaging (MMAP) technology is also increasing.
In development of digital and mixed signal designs (with both digital and analog circuits in the product) as well as RF products, the layout of the package substrate on BGA packages can be critical. Performance is impacted by trace length, substrate dielectric constant variation, trace matching, coupling effects, bond wire lengths, bond wire spacing, and loop radius. For flip chip product packages with dense bump arrays, the trace pitch requirements are tighter and routings are limited in the die bump array area.
Packages generally have two levels. The first level of packaging details the attachment of the die to the package substrate. The substrate acts as an interposer. The second level of packaging details the attachment of the package formed to a printed circuit board. One type of second level attachment of the package includes a plurality of either balls, pins, or lands formed in an array and disposed on a major surface of a substrate. The balls, pins or lands connect the semiconductor package to a printed circuit board or the like. A typical package may have from tens to over a thousand solder balls, pins or lands in the array. The die is assembled to a matching array of conductive pads or pin receiving openings.
In the case of a BGA package the die pads are connected to the substrate by “flip chip” or “wire bond” technology and connected to circuitry on a circuit board through the balls attached to the substrate. In the case of flip chip attachment, heat is applied to reflow the solder bumps to place the die to the substrate, thereby wetting the pads on the substrate and, once cooled, forming electrical connections between the package and the semiconductor device contained in the package. For wire bond connection, the die is typically glued to the substrate and the die bond pads are connected to the package substrate using gold wire. For connection to the circuit board to which the package is mounted, solder balls are attached to the substrate to printed pads on the substrate. Heat is applied to reflow the solder balls, thereby wetting the pads on the substrate and board, and once cooled, forming electrical connections between the package and the printed circuit board.
In the case of a pin grid array, the pins are connected to openings in the printed circuit board, such as the drill hole vias. The pins are soldered into place once the package has been inserted into the board.
In the case of a land grid array, the lands are directly soldered on the printed circuit board using solder paste or connected to the board using specially designed socket.
The description set out herein illustrates the various embodiments of the invention and such description is not intended to be construed as limiting in any manner.